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CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM FEATURES
s SPI bus compatible s Low power CMOS technology s 2.5V to 6.0V operation s Self-timed write cycle with auto-clear s Hardware reset pin s Hardware and software write protection
H
GEN FR ALO
EE
LE
A D F R E ETM
s Commercial, industrial and automotive
temperature ranges
s Power-up inadvertant write protection s RDY/BSY pin for end-of-write indication BSY s 1,000,000 program/erase cycles s 100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM which is configured as 64/128/256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC10/20/40 is manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, SOIC and TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC RDY/BUSY RESET GND
SOIC Package (J, W)
RDY/BUSY VCC CS SK 1 2 3 4 8 7 6 5 RESET GND DO DI
TSSOP Package (U, Y)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC RDY/BUSY RESET GND
SOIC Package (S, V)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC RDY/BUSY RESET GND
TSSOP Package (UR, YR)
RDY/BUSY VCC CS SK 1 2 3 4 8 7 6 5 RESET GND DO DI
PIN FUNCTIONS
Pin Name CS SK DI DO VCC GND RESET RDY/BUSY Function Chip Select Clock Input Serial Data Input Serial Data Output +2.5V to +6.0V Power Supply Ground Reset Ready/BUSY Status
BLOCK DIAGRAM
VCC GND
MEMORY ARRAY 64/128/256 x 16
ADDRESS DECODER
DATA REGISTER DI RESET CS MODE DECODE LOGIC OUTPUT BUFFER
SK
CLOCK GENERATOR
DO
RDY/BUSY
64LC10/20/40 F02
(c) 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1021, Rev. B
CAT64LC10/20/40
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to Ground(1) ............ -2.0V to +VCC +2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 1,000,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(3) VZAP(3) ILTH(3)(4)
CAPACITANCE (TA = 25C, f= 1.0 MHz, VCC =6.0V) Symbol CI/O(3) CIN
(3)
Test Input/Output Capacitance (DO, RDY/BSY) Input Capacitance (CS, SK, DI, RESET)
Max. 8 6
Units pF pF
Conditions VI/O = 0V VIN = 0V
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
Doc. No. 1021, Rev. B
2
CAT64LC10/20/40
D.C. OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, unless otherwise specified. Limits Sym. ICC Parameter Operating Current 2.5V Min. Typ. Max. 0.4 1 2 3 1 2 10 -0.1 VCC x 0.7 -0.1 VCC x 0.8 2.5V 6.0V VCC - 0.3 VCC - 0.3 2.4 VOL(1) Low Level Output Voltage 2.5V 6.0V 0.4 0.4 VCC x 0.3 VCC + 0.5 VCC x 0.2 VCC + 0.5 Units mA mA mA mA A A A V V V V V V V V V IOH = -10A IOH = -10A IOH = -400A IOL = 10A IOL = 2.1mA VIN = GND or VCC CS = VCC VIN = GND to VCC VOUT = GND to VCC Test Conditions fSK = 250 kHz fSK = 1 MHz
EWEN, EWDS, READ 6.0V ICCP Program Current 2.5V 6.0V ISB(1) ILI ILO VIL VIH VIL VIH Standby Current Input Leakage Current Output Leakage Current Low Level Input Voltage, DI High Level Input Voltage, DI Low Level Input Voltage, CS, SK, RESET High Level Input Voltage, CS, SK, RESET
VOH(1) High Level Output Voltage
Note: (1) VOH and VOL spec applies to READY/BUSY pin also
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Doc. No. 1021, Rev. B
CAT64LC10/20/40
A.C. OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, unless otherwise specified. Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(2) tCSMIN tSKHI Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High Impendance Minimum CS High Time Minimum SK High Time 2.5V 4.5V-6.0V tSKLOW Minimum SK Low Time 2.5V 4.5V-6.0V tSV fSK Output Delay to Status Valid Maximum Clock Frequency 2.5V 4.5V-6.0V tRESS tRESMIN tRESH tRC Reset to CS Setup Time Minimum RESET High Time RESET to READY Hold Time Write Recovery 250 1000 0 250 0 100 ns ns ns ns 250 1000 400 1000 400 500 ns kHz ns Min. 100 100 200 200 300 300 500 Typ. Max. Units ns ns ns ns ns ns ns ns ns
POWER-UP TIMING(1)(3) Symbol tPUR tPUW Parameter Power-Up to Read Operation Power-Up to Program Operation Min. Max. 10 1 Units s ms
WRITE CYCLE LIMIITS Symbol tWR Parameter Program Cycle Time 2.5V 4.5V-6.0V Min. Max. 10 5 Units ms
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) This parameter is sampled but not 100% tested. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Doc. No. 1021, Rev. B
4
CAT64LC10/20/40
INSTRUCTION SET Instruction Read 64LC10 64LC20 64LC40 Write 64LC10 64LC20 64LC40 Write Enable Write Disable [Write All Locations](1) Opcode 10101000 10101000 10101000 10100100 10100100 10100100 10100011 10100000 10100001 Address A5 A4 A3 A2 A1 A0 0 A6 A5 A4 A3 A2 A1 A0 0 0 Data D15 - D0 D15 - D0 D15 - D0 D15 - D0 D15 - D0 D15 - D0
A7 A6 A5 A4 A3 A2 A1 A0 A5 A4 A3 A2 A1 A0 0 A6 A5 A4 A3 A2 A1 A0 0 0
A7 A6 A5 A4 A3 A2 A1 A0 XXXXXXXX XXXXXXXX XXXXXXXX
D15-D0
Figure 1. A.C. Testing Input/Output Waveform (2)(3(4) (CL = 100 pF)
VCC x 0.8 INPUT PULSE LEVELS VCC x 0.2 VCC x 0.3 VCC x 0.7 REFERENCE POINTS
Note: (1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications. (2) Input Rise and Fall Times (10% to 90%) < 10 ns. (3) Input Pulse Levels = VCC x 0.2 and VCC x 0.8. (4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.
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Doc. No. 1021, Rev. B
CAT64LC10/20/40
DEVICE OPERATION
The CAT64LC10/20/40 is a 1K/2K/4K-bit nonvolatile memory intended for use with all standard controllers. The CAT64LC10/20/40 is organized in a 64/128/256 x 16 format. All instructions are based on an 8-bit format. There are four 16-bit instructions: READ, WRITE, EWEN, and EWDS. The CAT64LC10/20/40 operates on a single power supply ranging from 2.5V to 6.0V and it has an onchip voltage generator to provide the high voltage needed during a programming operation. Instructions, addresses Figure 2. Sychronous Data Timing and data to be written are clocked into the DI pin on the rising edge of the SK clock. The DO pin is normally in a high impedance state except when outputting data in a READ operation or outputting RDY/BSY status when polled during a WRITE operation. The format for all instructions sent to this device includes a 4-bit start sequence, 1010, a 4-bit op code and an 8bit address field or dummy bits. For a WRITE operation,
RESET tRESS SK tDIS DI tCSS CS tPD0,tPD1 DO tRC RDY/BUSY tRESH tSV tHZ tSV tCSH tCSMIN tDIH tSKLOW tSKHI
Figure 3. Read Instruction Timing
RESET
SK
CS
DI
1
0
1
0
1
0
0
0
ADDRESS*
DO HIGH
D15 D14
D1 D0
RDY/BUSY
* Please check the instruction set table for address
Doc. No. 1021, Rev. B
6
CAT64LC10/20/40
a 16-bit data field is also required following the 8-bit address field. The CAT64LC10/20/40 requires an active LOW CS in order to be selected. Each instruction must be preceded by a HIGH-to-LOW transition of CS before the input of the 4-bit start sequence. Prior to the 4-bit start sequence (1010), the device will ignore inputs of all other logical sequence.
Read Upon receiving a READ command and address (clocked into the DI pin), the DO pin will output data one tPD after the falling edge of the 16th clock (the last bit of the address field). The READ operation is not affected by the RESET input. Write After receiving a WRITE op code, address and data, the device goes into the AUTO-Clear cycle and then the
Figure 4. Write Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO
RDY/BUSY
* Please check instruction set table for address
Figure 5. Ready/BUSY Status Instruction Timing BUSY
RESET LOW
SK
CS WRITE INSTRUCTION DI NEXT INSTRUCTION
DO HIGH RDY/BUSY
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Doc. No. 1021, Rev. B
CAT64LC10/20/40
WRITE cycle. The RDY/BSY pin will output the BUSY status (LOW) one tSV after the rising edge of the 32nd clock (the last data bit) and will stay LOW until the write cycle is complete. Then it will output a logical "1" until the next WRITE cycle. The RDY/BSY output is not affected by the input of CS. An alternative to get RDY/BSY status is from the DO pin. During a write cycle, asserting a LOW input to the CS pin will cause the DO pin to output the RDY/BSY status. Bringing CS HIGH will bring the DO pin back to a high impedance state again. After the device has completed a WRITE cycle, the DO pin will output a logical "1" when
the device is deselected. The rising edge of the first "1" input on the DI pin will reset DO back to the high impedance state again. The WRITE operation can be halted anywhere in the operation by the RESET input. If a RESET pulse occurs during a WRITE operation, the device will abort the operation and output a READY status. NOTE: Data may be corrupted if a RESET occurs while the device is BUSY. If the reset occurs before the BUSY period, no writing will be initiated. However, if RESET occurs after the BUSY period, new data will have been written over the old data.
Figure 6. RESET During BUSY Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO tWR RDY/BUSY
* Please check instruction set table for address
Figure 7. EWEN Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
0
1
1
DO
HIGH-Z
RDY/BUSY
HIGH
5064 FHD F09
Doc. No. 1021, Rev. B
8
CAT64LC10/20/40
RESET The RESET pin, when set to HIGH, will reset or abort a WRITE operation. When RESET is set to HIGH while the WRITE instruction is being entered, the device will not execute the WRITE instruction and will keep DO in HighZ condition. When RESET is set to HIGH, while the device is in a clear/write cycle, the device will abort the operation and will display READY status on the RDY/BSY pin and on the DO pin if CS is low. The RESET input affects only the WRITE and WRITE ALL operations. It does not reset any other operations such as READ, EWEN and EWDS. Figure 8. EWDS Instruction Timing
RESET
ERASE/WRITE ENABLE and DISABLE The CAT64LC10/20/40 powers up in the erase/write disabled state. After power-up or while the device is in an erase/write disabled state, any write operation must be preceded by an execution of the EWEN instruction. Once enabled, the device will stay enabled until an EWDS has been executed or a power-down has occured. The EWDS is used to prevent any inadvertent overwriting of the data. The EWEN and EWDS instructions have no affect on the READ operation and are not affected by the RESET input.
SK
CS
DI
1
0
1
0
0
0
0
0
DO
HIGH-Z
HIGH RDY/BUSY
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Doc. No. 1021, Rev. B
CAT64LC10/20/40
ORDERING INFORMATION
P: PDIP S: SOIC (JEDEC) J: SOIC (JEDEC) U: TSSOP UR: TSSOP (Rotated) L: PDIP (Lead free, Halogen free) V: SOIC (JEDEC) (Lead free, Halogen free) W: SOIC (JEDEC) (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) YR: TSSOP (Rotated) (Lead free, Halogen free)
Notes: (1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 1021, Rev. B
10
CAT64LC10/20/40
PACKAGING INFORMATION 8-LEAD TSSOP (U)
3.0 + 0.1 -A8 5
7.72 TYP
6.4 4.4 + 0.1 -B(1.78 TYP) 3.2
4.16 TYP
0.42 TYP 0.65 TYP 0.2 C B A 1
PIN #1 IDENT.
4
ALL LEAD TIPS
LAND PATTERN RECOMMENDATION
SEE DETAIL A 1.1 MAX TYP 0.1 C
ALL LEAD TIPS
0.09 - 0.20 TYP (0.9)
-C0.10 + 0.05 TYP 0.65 TYP 0.19 - 0.30 TYP 0.3 M A B S C S
GAGE PLANE 0.25
0 o- 8 o
0.6+0.1
SEATING PLANE
DETAIL A
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Doc. No. 1021, Rev. B
CAT64LC10/20/40
REVISION HISTORY
Date 9/3/2004 Rev. B Reason Added Green packages in all areas Updated DC Operating Characteristics table & notes
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
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Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Publication #: Revison: Issue date:
1021 B 9/3/04
Doc. No. 1021, Rev. B
12
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